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| UT54ACS374/UT54ACTS374 Radiation-Hardened Octal D-Type Flip-Flops with Three-State Outputs FEATURES 8 latches in a single package Three-state bus-driving true outputs Full parallel access for loading radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack DESCRIPTION The UT54ACS374 and the UT54ACTS374 are non-inverting octal D type flip-flops with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers. The eight flip-flops are edge triggered D-type flip-flops. On the positive transition of the clock the Q outputs will follow the data (D) inputs. An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without the need for interface or pull-up components. The output control OC does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OC L L L H L X CLK nD H L X X OUTPUT nQ H L nQ0 Z PINOUTS 20-Pin DIP Top View OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 20-Lead Flatpack Top View OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK LOGIC SYMBOL OC CLK (1) (11) EN C1 1D (3) (4) 2D 3D (7) (8) 4D 5D (13) 6D (14) 7D (17) 8D (18) 1D (2) 1Q (5) 2Q (6) 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 223 RadHard MSI Logic UT54ACS374/UT54ACTS374 LOGIC DIAGRAM 8D (18) 7D (17) 6D (14) 5D (13) 4D (8) 3D (7) 2D (4) 1D (3) CLK OC (11) (1) DC Q DC Q DC Q DC Q DC Q DC Q DC Q DC Q (19) 8Q 7Q (16) (15) 6Q (12) 5Q 4Q (9) 3Q (6) 2Q (5) (2) 1Q RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATING SYMBOL VDD VI/O TSTG TJ TLS JC PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation LIMIT -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 10 1 UNITS V V C C C C/W mA W II PD Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 224 UT54ACS374/UT54ACTS374 RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V xC 225 RadHard MSI Logic UT54ACS374/UT54ACTS374 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Three-state output leakage current Short-circuit output current 2 ,4 ACTS/ACS Output current10 (Sink) IOH Output current10 (Source) Ptotal IDDQ IDDQ Power dissipation 2, 8, 9 Quiescent Supply Current Quiescent Supply Current Delta ACTS VIN = VDD or VSS IOL = 8.0mA IOL = 100 A IOH = -8.0mA IOH = -100 A VO = VDD and VSS VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 Output capacitance 5 = 1MHz @ 0V = 1MHz @ 0V 15 15 pF pF 1.9 10 1.6 mW/ MHz A mA -8 mA .7VDD VDD - 0.25 -20 20 .5VDD .7VDD -1 1 CONDITION MIN MAX 0.8 .3VDD UNIT V VIH V IIN VOL A 0.40 0.25 V VOH V IOZ IOS IOL A -200 8 200 mA mA RadHard MSI Logic 226 UT54ACS374/UT54ACTS374 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 227 RadHard MSI Logic UT54ACS374/UT54ACTS374 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ fMAX tSU tH tW CLK to Qn CLK to Qn OC low to Qn active OC low to Qn active OC high to Qn three-state OC high to Qn three-state Maximum clock frequency Data setup time before CLK Data hold time after CLK Minimum pulse width CLK high, CLK low 5 2 7 PARAMETER MINIMUM 1 1 1 1 1 1 MAXIMUM 15 18 13 13 11 12 71 UNIT ns ns ns ns ns ns MHz ns ns ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 228 |
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